The new chip developed by a research team under the lead of Anantha Chandrakasan Vannevar (Bush Professor of Electrical Engineering and Computer Science at MIT) solves some of the obstacles for voice recognition to become usual in IOT devices and wearables. Among them the new chip enables power savings of 90 to 99% in a real world application.<\/p>\n
A cellphone running speech-recognition software might require about 1 watt of power, while the new chip requires between 0.2 and 10 milliwatts, depending on the number of words it has to recognize.<\/p>\n
\u00abSpeech input will become a natural interface for many wearable applications and intelligent devices,\u201d says Anantha Chandrakasan, the Vannevar Bush Professor of Electrical Engineering and Computer Science at MIT, whose group developed the new chip. \u201cThe miniaturization of these devices will require a different interface than touch or keyboard. It will be critical to embed the speech functionality locally to save system energy consumption compared to performing this operation in the cloud.\u00bb<\/p>\n
\u201cFor the next generation of mobile and wearable devices, it is crucial to enable speech recognition at ultralow power consumption,\u201d said Marian Verhelst, a professor of microelectronics at the Catholic University of Leuven in Belgium. \u201cThis is because there is a clear trend toward smaller-form-factor devices, such as watches, earbuds, or glasses, requiring a user interface which can no longer rely on touch screen. Speech offers a very natural way to interface with such devices.\u201d<\/p>\n
Price, Chandrakasan, and Jim Glass, a senior research scientist at MIT\u2019s Computer Science and Artificial Intelligence Laboratory, described the new chip in a paper Price presented last week at the International Solid-State Circuits Conference.<\/p>\n
Power savings through filtering ambient noise<\/strong><\/span><\/p>\n even the most power-efficient speech recognition system would quickly drain a device\u2019s battery if it ran without interruption. So the chip also includes a simpler \u201cvoice activity detection\u201d circuit that monitors ambient noise to determine whether it might be speech. If the answer is yes, the chip fires up the larger, more complex speech-recognition circuit.<\/p>\n Power savings based on chip local stores<\/strong><\/span><\/p>\n A voice-recognition network is too big to fit in a chip\u2019s onboard memory, which is a problem because going off-chip for data is much more energy intensive than retrieving it from local stores. So the MIT researchers\u2019 design concentrates on minimizing the amount of data that the chip has to retrieve from off-chip memory.<\/p>\n Power savings through bandwith management<\/strong><\/span><\/p>\n The first step in minimizing the new chip\u2019s memory bandwidth is to compress the weights associated with each node. The data are decompressed only after they\u2019re brought on-chip.<\/p>\n A node in the middle of a neural network might receive data from a dozen other nodes and transmit data to another dozen. Each of those two dozen connections has an associated \u201cweight,\u201d a number that indicates how prominently data sent across it should factor into the receiving node\u2019s computations.<\/p>\n Besides, the chip also exploits the fact that, with speech recognition, wave upon wave of data must pass through the network. The research was funded through the Qmulus Project, a joint venture between MIT and Quanta Computer, and the chip was prototyped through the Taiwan Semiconductor Manufacturing Company\u2019s University Shuttle Program.<\/p>\n Image over the headline.- <\/strong>\u00a9 Eastwind.<\/span><\/p>\n <\/p>\n","protected":false},"excerpt":{"rendered":" The new chip developed by a research team under the lead of Anantha Chandrakasan Vannevar (Bush Professor of Electrical Engineering and Computer Science at MIT) solves some of the obstacles for voice recognition to become usual in IOT devices and wearables. Among them the new chip enables power savings of 90 to 99% in a …<\/p>\n
\nThe incoming audio signal is split up into 10-millisecond increments, each of which must be evaluated separately.
\nThe MIT researchers\u2019 chip brings in a single node of the neural network at a time, but it passes the data from 32 consecutive 10-millisecond increments through it.
\nThe chip ends up requiring a sizable onboard memory circuit for its intermediate computations. But it fetches only one compressed node from off-chip memory at a time, keeping its power requirements low.<\/p>\n